1. Field of the Invention
The present invention relates to a ferroelectric capacitor.
2. Description of the Related Art
A ferroelectric memory is a kind of nonvolatile memory. A mechanism of polarization of the ferroelectric capacitor is described in a reference 1: “Ferroelectric thin film integration technology” Tadashi Shiosaki, Feb. 28, 1992, Science Forum Inc, pp. 205-213. Also, a device structure is described in a reference 2: Japanese Patent Laid-Open No. 5-82802 and a reference 3: Japanese Patent Laid-Open No. 2001-156263.
In a conventional ferroelectric memory, one terminal of a ferroelectric capacitor is connected to a drive line and the other terminal of the ferroelectric capacitor is connected to a bit line via a select transistor as described in reference 2. The polarized condition of the ferroelectric capacitor represents the data of a memory cell. For example, a condition that the ferroelectric capacitor is polarized positive can represent data of “1” and a condition that the ferroelectric capacitor is polarized negative can represent data of “0”.
When the drive line is high level and the select transistor turns on, a voltage of the bit line changes responsive to the polarization condition of the ferroelectric capacitor. The voltage of the bit line is amplified by a sense amplifier and outputted.
The ferroelectric memory is a destructive read type memory. Therefore, a rewriting step is needed for every read step. The rewriting step is performed by supplying the amplified voltage to the bit line.
Recently, fast read ferroelectric memories are desired. The inventor has thus considered the causes of the read time of the ferroelectric memory being slow.
FIG. 1 is a plot showing a relationship between a delay time and a read margin. The delay time shows a time from when a read voltage is applied between each of the terminals of the ferroelectric capacitor, to when the sense amplifier is operated. The read margin is a voltage difference between a read voltage representing a data “1” as stored in the ferroelectric capacitor and a read voltage representing a data “0” as stored in the ferroelectric capacitor. A high level is shown by “1” and a low level is shown by “0”. In FIG. 1, a vertical axis shows the read margin and a horizontal axis shows the delay time. FIG. 1 shows cases of read voltage of 2V, 3V and 3.6V.
For example, if a margin of 0.4V is needed, a delay time is 400 ns, 60 ns and 40 ns respectively for each read voltage 2V, 3V and 3.6V.
FIG. 2(A) to FIG. 2(C) are plots showing a relationship between a delay time and a voltage of the bit line. In FIG. 2(A) to FIG. 2(C), a vertical axis shows the voltage of the bit line and a horizontal axis shows the delay time. A lowest voltage from the memory cell which is stored as a “1” value and a highest voltage from the memory cell which is stored as a “0” value are shown in FIG. 2(A) to FIG. 2(C). FIG. 2(A) to FIG. 2(C) show a plot for writing voltage of 2V, 3V and 3.6V respectively.
If the stored data is “1”, the read voltage is dependent largely on the time. If the stored data is “0”, the read voltage is not dependent so much on the time. Data “1” is read with a polarization reversal and data “0” is read without the polarization reversal. That is, the delay time is dependent on the polarization reversal time.
FIG. 3(A) and FIG. 3(B) are plots showing a relationship between the delay time and the voltage of the bit line. FIG. 3(A) shows curves of data “0” of FIG. 2(A) to FIG. 2(C), and FIG. 3(B) shows curves of data “1” of FIG. 2(A) to FIG. 2(C).
If data is “0”, the relationship between the delay time and the voltage of the bit line is not dependent on the read voltage. If data is “1”, the relationship between the delay time and the voltage of the bit line is largely dependent on the read voltage. Therefore, using high read voltage is preferable for fast reading time of the ferroelectric capacitor.
However, using high voltage for reading the ferroelectric memory increases power consumption. If the voltage applied between each terminal of the ferroelectric capacitor is increased, field intensity at the ferroelectric capacitor is increased. As a result, reliability of the ferroelectric layer of the ferroelectric capacitor is decreased.
FIG. 4(A) to FIG. 4(C) are views showing a mechanism of the polarization of the ferroelectric capacitor. First, a voltage is applied with a bottom electrode 1201 and a top electrode 1203. Then, cores 1204 for inverting the polarization are generated in a ferroelectric layer 1202 as shown in FIG. 4(A). The cores 1204 are generated in a boundary face between the bottom electrode 1201 and the ferroelectric layer 1202 and a boundary face between the top electrode 1203 and the ferroelectric layer 1202. Then, the cores 1204 are extended to the other electrode as shown in FIG. 4(B). Then, the cores 1204 are extended in horizontal direction and combined with each other as shown in FIG. 4(C). As a result, the inversion of the polarization of the ferroelectric capacitor is completed.
In the polarization operation, an extending speed of the cores in a vertical direction is fast, and an extending speed of the cores in a horizontal direction is slow. Therefore, a time for the polarization operation is dependent largely on the extending time in the horizontal direction.